CMOS circuits for high speed serial data communication

With the fast growth of computer power and network services, high performance peripherals and interfaces are being developed to meet the system needs. High speed serial data communication devices are especially important and much effort has been spent to increase the bandwidth, reduce the cost, lower the power dissipation and improve the level of integration. Driven by these motivations, various commercial products with data rates ranging from several hundred Mbps to several Gbps have been developed in GaAs or Si bipolar technologies. Potentially less expensive silicon CMOS implementation of these functions are presently begin investigated and is the focus of this work. The serial data link has been dominant in network connections, such as Ethernet, FDDI or ATM, and will find even wider application in the future. This work focuses on the implementation of some basic building blocks for very high speed serial data communication using CMOS technology. At the transmitter end, a novel parallel-toserial converter is presented, whose core is a 5 by 4 register matrix which combines the selection and shift schemes for conversion. Using this architecture, a pipelined data loading is applied to multiple data paths running at sub-multiple of the data rate. This significantly reduces the dynamic power dissipation and eases the system design. The special clock strategy to drive the converter is investigated in this work. SPICE simulations and a chip layout of this method are presented. Various design and layout considerations are also discussed. At the receiver end, a clock recovery circuit based on a charge pump phase locked loop is proposed. The VCO has an internal feedback loop to adjust the duty cycle at different frequency. A simple conventional phase detector with a limited output swing is used to achieve the high working frequency. A modified symmetrical charge pump circuit improves linearity of the output current versus the input UP and DOWN signal. Some characteristics such as impulse capture range and